1. Field of the Invention
The present invention relates to electronic semiconductor devices, and, more particularly, to methods of fabrication of self-aligned MESFET and vertical bipolar transistors.
2. Description of the Related Art
Metal semiconductor field effect transistors (MESFETs) are commonly used in gallium arsenide (GaAs) digital integrated circuits and one of the factors restricting switching speeds is the parasitic source and drain resistance. The parasitic resistances can be lessened by decreasing the gate-to-source and gate-to-drain distances to much less than 1 .mu.m; and such small distances typically require some sort of self-alignment of the gate with respect to the source and drain. Similarly, in vertical bipolar transistors (silicon and GaAs) the base resistance limits high frequency response but it can be lessened by decreasing the distance between the emitter and the external base contact. Again, self-alignment of the emitter with respect to the base contact is required for distance much less than 1 .mu.m.
Several self-alignment method have been proposed. For example, T. Sakai et al, Prospects of SST Technology for High Speed LSI, 1985 IEDM Tech. Digest 18, illustrates a vertical silicon bipolar transistor with emitter and submicron width base electrode, and base and emitter contacts fabricated by a self-aligned technique using only one optical mask. M. Hagio et al, A New Self-Align Technology for Low Noise GaAs MESFET's--Sidewall-Assisted Pattern Inversion Technology --, 1984 IEDM Tech. Digest 194, covers a dummy SiO.sub.2 gate with 0.1 .mu.m of PCVD Si.sub.3 N.sub.4, implants through the nitride to form the source and drain with the dummy gate and the vertical sidewalls of nitride masking the implant; thus the thickness of the nitride determines the distance from the dummy gate to the source and drain; and lastly the dummy gate is replaced with a Ti/Al gate. K. Yamasaki et al, Self-Align Implantation for n.sup.+ -Layer Technology (SAINT) for High-Speed GaAs ICs, 18 Elec. Lett. 119 (1982), uses a tri-level resist made of FPM, sputtered silicon dioxide, and photoresist and patterns the top level photoresist to define a dummy gate in the silicon dioxide and FPM; the etching to form the dummy gate undercuts the FPM so the silicon dioxide provides an overhang; the dummy gate (silicon dioxide overhang) masks a source and drain implant which is followed by a second sputtering deposition of silicon dioxide that does get under the overhang; thus when the dummy gate is removed by dissolution of the FPM, the opening the silicon dioxide leads to a metal gate aligned with the source and drain. The distance from gate to source and drain is determined by the undercut of the FPM during the dummy gate formation etch.
However, these self-alignment methods have problems such as complicated multi-level resist processing, tricky SiO.sub.2 sidewall isolation, or critical use of high-temperature stable refractory contacts. In particular, the SAINT method has a resist structure that does not stand up well to temperature during the SiO.sub.2 sputter deposition and requires a difficult sidewall removal of SiO.sub.2 that must avoid undercutting the FPM and etching nitride underneath. One variation that avoids the difficult sidewall SiO.sub.2 removal is the substitution of SiO.sub.2 evaporation for the second SiO.sub.2 sputter deposition; but SiO.sub.2 evaporation is itself a difficult step.